1. Field of the Invention
The present invention relates generally to die-planarization techniques and, more specifically, to placement of fill tiles in an interconnect structure of an integrated circuit (IC).
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention(s). Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
Chemical-mechanical polishing (CMP) is a planarization technique that is widely used in IC fabrication. A surface of the die subjected to CMP undergoes (i) chemical reactions induced by a slurry and (ii) mechanical abrasion by a CMP pad. Although CMP pads and slurries have improved significantly over the years, the smoothness of the resulting die surface is still not perfect and significant post-CMP surface-topography variations can occur for some circuit-layout patterns. As successive metal and dielectric layers are being deposited over a die and subjected to CMP during the fabrication of an interconnect structure for the IC, the post-CMP surface-topology variations translate into thickness variations within the interconnect levels and inter-level dielectric (ILD). These thickness variations might be detrimental to the IC yield and/or performance because they disturb lithographic imaging and throw off the electrical parameters (such as resistance and/or capacitance) of the interconnect structure.
One design for manufacturability (DFM) technique that improves surface planarity uses insertion of special metal patterns (often referred to as fills, dummies, or waffles) into the circuit layout to make the density distribution over the die as uniform as possible. Since the CMP material-removal rate is a function of local material density, the metal fill helps to reduce the above-described thickness variations. However, if not appropriately designed, the metal fill might have a net detrimental effect on the IC yield and/or performance, e.g., by adversely affecting certain sensitive signals in terms of their timing and/or integrity.